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| enum | {
esphome::mpl3115a2::MPL3115A2_REGISTER_STATUS = (0x00),
esphome::mpl3115a2::MPL3115A2_REGISTER_PRESSURE_MSB = (0x01),
esphome::mpl3115a2::MPL3115A2_REGISTER_PRESSURE_CSB = (0x02),
esphome::mpl3115a2::MPL3115A2_REGISTER_PRESSURE_LSB = (0x03),
esphome::mpl3115a2::MPL3115A2_REGISTER_TEMP_MSB = (0x04),
esphome::mpl3115a2::MPL3115A2_REGISTER_TEMP_LSB = (0x05),
esphome::mpl3115a2::MPL3115A2_REGISTER_DR_STATUS = (0x06),
esphome::mpl3115a2::MPL3115A2_OUT_P_DELTA_MSB = (0x07),
esphome::mpl3115a2::MPL3115A2_OUT_P_DELTA_CSB = (0x08),
esphome::mpl3115a2::MPL3115A2_OUT_P_DELTA_LSB = (0x09),
esphome::mpl3115a2::MPL3115A2_OUT_T_DELTA_MSB = (0x0A),
esphome::mpl3115a2::MPL3115A2_OUT_T_DELTA_LSB = (0x0B),
esphome::mpl3115a2::MPL3115A2_WHOAMI = (0x0C),
esphome::mpl3115a2::MPL3115A2_BAR_IN_MSB = (0x14),
esphome::mpl3115a2::MPL3115A2_BAR_IN_LSB = (0x15)
} |
| | MPL3115A2 registers. More...
|
| |
| enum | { esphome::mpl3115a2::MPL3115A2_REGISTER_STATUS_TDR = 0x02,
esphome::mpl3115a2::MPL3115A2_REGISTER_STATUS_PDR = 0x04,
esphome::mpl3115a2::MPL3115A2_REGISTER_STATUS_PTDR = 0x08
} |
| | MPL3115A2 status register bits. More...
|
| |
| enum | { esphome::mpl3115a2::MPL3115A2_PT_DATA_CFG = 0x13,
esphome::mpl3115a2::MPL3115A2_PT_DATA_CFG_TDEFE = 0x01,
esphome::mpl3115a2::MPL3115A2_PT_DATA_CFG_PDEFE = 0x02,
esphome::mpl3115a2::MPL3115A2_PT_DATA_CFG_DREM = 0x04
} |
| | MPL3115A2 PT DATA register bits. More...
|
| |
| enum | {
esphome::mpl3115a2::MPL3115A2_CTRL_REG1 = (0x26),
esphome::mpl3115a2::MPL3115A2_CTRL_REG2 = (0x27),
esphome::mpl3115a2::MPL3115A2_CTRL_REG3 = (0x28),
esphome::mpl3115a2::MPL3115A2_CTRL_REG4 = (0x29),
esphome::mpl3115a2::MPL3115A2_CTRL_REG5 = (0x2A)
} |
| | MPL3115A2 control registers. More...
|
| |
| enum | {
esphome::mpl3115a2::MPL3115A2_CTRL_REG1_SBYB = 0x01,
esphome::mpl3115a2::MPL3115A2_CTRL_REG1_OST = 0x02,
esphome::mpl3115a2::MPL3115A2_CTRL_REG1_RST = 0x04,
esphome::mpl3115a2::MPL3115A2_CTRL_REG1_RAW = 0x40,
esphome::mpl3115a2::MPL3115A2_CTRL_REG1_ALT = 0x80,
esphome::mpl3115a2::MPL3115A2_CTRL_REG1_BAR = 0x00
} |
| | MPL3115A2 control register bits. More...
|
| |
| enum | {
esphome::mpl3115a2::MPL3115A2_CTRL_REG1_OS1 = 0x00,
esphome::mpl3115a2::MPL3115A2_CTRL_REG1_OS2 = 0x08,
esphome::mpl3115a2::MPL3115A2_CTRL_REG1_OS4 = 0x10,
esphome::mpl3115a2::MPL3115A2_CTRL_REG1_OS8 = 0x18,
esphome::mpl3115a2::MPL3115A2_CTRL_REG1_OS16 = 0x20,
esphome::mpl3115a2::MPL3115A2_CTRL_REG1_OS32 = 0x28,
esphome::mpl3115a2::MPL3115A2_CTRL_REG1_OS64 = 0x30,
esphome::mpl3115a2::MPL3115A2_CTRL_REG1_OS128 = 0x38
} |
| | MPL3115A2 oversample values. More...
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| |
